1. Field of the Invention.
The present invention relates generally to erasable programmable logic array devices and, more particularly, to an integrated read and programming row driver for such a device. The present invention is an improvement upon current erasable programmable logic device (EPLD) technology.
2. Prior Art
Prior art programmable logic array devices using electrically programmable read only memories (EPROMs) are described in U.S. Pat. No. 4,609,986 and U.S. Pat. No. 4,617,479. Typically in these prior art EPROM devices, there is a pitch constrained area in which certain circuitry must be located for optimum device operation. A pitch constrained area is a limiteed section of the device occupied by the memory cells and associated circuitry which requires its physical placement to be proximate to the memory cells. Typically, the pitch constrained area is comprised of the memory cells and critical circuitry which must operate adjacent and not physically distant from the memory cells. Typically, read/programming circuitry, architecture circuits, and macrocells to process outputs from the array must reside within this pitch constrained area. The adjacency is necessary to reduce capacitance and lead length in order to increase the speed of performance of the device.
A measure of effective utility of an EPROM device is the density of the memory cells. Typically an EPROM device, when used in EPLD technology, will have its memory cells arranged in a two dimensional array which is bounded by its associated read and programmable circuits. To achieve higher density, many devices incorporate a plurality of arrays in a single semiconductor integrated circuit chip.
By these prior art designs using multiple arrays, some circuitry was duplicated. One solution, which is discussed infra, combines the read circuitry for the two arrays in the row divers. It is appreciated that a further reduction in the size of the associated circuitry will permit additional memory cells to be disposed in the pitch constrained area.